Well known are RAMs which have at least one address port and include storage elements (core cells). In a paper by A. L. Silburt et al entitled "A 180-MHz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, March 1993, p. 222, at 227 shows various arrays of RAM storage elements.
In a paper by B. Nadeau-Dostie et al entitled "Serial Interfacing for Embedded-Memory Testing", IEEE Design & Test of Computers, April 1990, p. 52 discloses BIST architecture and memory test.
In RAMs, the problem is to develop a practical, non-intrusive method for sensitizing shorts between bit lines from different ports.